Power Supply Decoupling

Power Decoupling and PDN Impedance

Intermittent resets, data errors, and unexplained noise are often power distribution problems. Adding decoupling capacitors can help, but only when you understand the frequency range you are trying to cover and the inductance in the connection path.

Decoupling is about maintaining low PDN impedance across the frequencies your load transients excite. Poor value selection or placement can create anti-resonance peaks that increase impedance at exactly the wrong frequencies.

Power distribution network (PDN) design is fundamentally an impedance problem, not a capacitance problem. Once you understand how to analyze and shape PDN impedance, you can place the right capacitors in the right locations and avoid the cycle of adding parts without solving the root cause.

It's About Impedance, Not Capacitance

Voltage droop: $\Delta V = I \times Z_{PDN}$. Your circuit demands current with nanosecond rise times. If the PDN impedance is too high at those frequencies, you get voltage droop, and your IC misbehaves.

"Add more caps" misses the point. You need low impedance at the frequencies that matter. A 100 µF capacitor does nothing at 100 MHz. It's a 100 µF inductor by then.

Capacitors Are Inductors Above Their SRF

Every real capacitor has parasitic inductance (ESL). At the self-resonant frequency (SRF), capacitive and inductive reactances cancel, leaving just ESR. Above the SRF, the cap becomes an inductor.

A 10 µF electrolytic might have an SRF around 1 MHz. Above that, it's useless for decoupling. That's why you need a range of values: bulk caps for low frequencies, small ceramics for high frequencies.

Target Impedance: Your Design Goal

$Z_{target} = \frac{V_{supply} \times Ripple\%}{I_{transient}}$

Example: 1.0V core rail, 3% tolerance, 5A transient = 6 mΩ target. That's aggressive. You need tight PDN design to hit that from DC to hundreds of MHz.

Plot your PDN impedance versus frequency. If it exceeds target anywhere in your frequency range, you'll have problems there. Most designs need bulk caps, MLCCs, and good plane capacitance together.

The capacitance value on the part number is only the beginning. Class 2 ceramic capacitors (X7R, X5R) offer high capacitance in small packages but lose capacitance with applied DC voltage, sometimes 50% or more at rated voltage. You have to derate for this. Class 1 ceramics (C0G/NP0) maintain stable capacitance but are limited to smaller values. Electrolytic capacitors provide bulk capacitance for low-frequency filtering but have high ESR and ESL, limiting their effectiveness at high frequencies. And don't forget that these capacitors age, shift with temperature, and can crack if the board flexes.

Placement: Every Millimeter Matters

Loop inductance kills high-frequency decoupling. A 5mm isolated trace can add up to ~5 nH (the worst-case ~1 nH/mm wire-in-air figure); a microstrip closely coupled to a return plane is closer to 0.3 to 0.5 nH/mm, which still works out to a couple of ohms at 100 MHz once you include the via spreading inductance. Either way, every millimeter and every via in the loop costs you headroom.

Place decoupling caps as close to IC power pins as physically possible. Use fat, short traces. Multiple vias in parallel. The cap that's 10mm away might as well not exist for high-frequency transients.

Putting capacitors in parallel isn't always as simple as it sounds. Different values in parallel can give you low impedance across a wide frequency range, but between the SRFs of different values, anti-resonance peaks can appear where impedance actually exceeds that of a single capacitor. This happens when the capacitive reactance of the larger cap resonates with the inductive reactance of the smaller one. Lower ESR makes these peaks sharper and taller. Sometimes you intentionally choose caps with higher ESR to damp the resonances.

At very high frequencies, the power/ground plane pair is your best decoupling element. Closely spaced planes form a parallel-plate capacitor with low inductance because the current path is wide and the spacing is tight. The capacitance per unit area is: $C = \frac{\epsilon_0 \epsilon_r A}{d}$, where $\epsilon_r$ is the dielectric constant, $A$ is area, and $d$ is spacing. For FR-4 with $\epsilon_r$ around 4.2 to 4.6, this yields roughly 0.37-0.41 pF/mm² at 0.1mm spacing. While this seems small, a 100mm x 100mm plane area provides about 4 nF of very low-inductance capacitance. More importantly, the plane pair's spreading inductance is much lower than the connection inductance of discrete caps, so it picks up where discrete decoupling runs out. Watch out for plane resonances at frequencies where the dimensions approach quarter wavelengths.

Vias matter more than you'd think. Each via adds inductance roughly equal to: $L_{via} \approx 0.2h[\ln(\frac{4h}{d}) + 1]$ nH, where $h$ is via height and $d$ is diameter. For a typical 1.6mm board with 0.3mm diameter vias, this yields about 1.2 nH per via. At high frequencies this inductance can dominate the connection path. Use multiple vias in parallel (inductance drops roughly as 1/N for N vias), larger via diameters, and shorter via lengths through build-up or buried via structures. Space vias at least one diameter apart so they carry current independently.

Multiple voltage rails sharing a ground plane can interact in ways you didn't plan for. Current from one domain creates voltage fluctuations in the shared ground that couple into other domains. Ferrite beads are sometimes used to isolate rails, but their high impedance at high frequencies can actually worsen transient response if not properly bypassed. Local regulation or filtering combined with adequate local decoupling for each domain usually works better.

An oscilloscope alone won't tell you the whole story. You can capture voltage transients, but probe bandwidth and connection inductance filter out high-frequency content, making problems look less severe than they are. A vector network analyzer (VNA) gives a more complete picture by directly measuring PDN impedance versus frequency. The two-port shunt-through method works well, but you need careful calibration and low-inductance probe connections to avoid measurement artifacts.

There's more to power noise than resistive voltage drops. Simultaneous switching noise (SSN) happens when multiple outputs switch at once, dumping large transient currents into the PDN. The resulting voltage fluctuations couple into analog circuits, create timing jitter in digital circuits, and radiate as EMI. The magnitude of SSN can be estimated as: $V_{SSN} = N \times L \times \frac{dI}{dt}$, where $N$ is the number of simultaneous switching outputs, $L$ is the total loop inductance, and $dI/dt$ is the current slew rate. This is why high-pin-count devices with fast edge rates need careful PDN design. Staggered switching, controlled slew rates, and differential signaling all help reduce SSN.

For the most demanding designs, embedded capacitance materials integrate thin dielectric layers into the PCB stackup, providing distributed capacitance with ultra-low inductance. Plain unfilled laminates around 25 µm thick give roughly 0.25 nF/cm²; ceramic-filled materials such as 3M's C-Ply family reach 1 to 2 nF/cm² with 10 to 15 µm dielectrics, and the thinnest grades push to around 3 nF/cm². It's more expensive, but it can replace dozens of discrete caps while delivering better high-frequency performance. Package-level and die-level decoupling push capacitance even closer to the noise source, though at added cost and manufacturing complexity.

Simulation helps, but only if your models are realistic. SPICE can predict impedance profiles and transient response, but garbage models give garbage results. Common mistakes: forgetting via inductance, using ideal capacitor models, and assuming perfect ground planes. Field solvers extract accurate parasitics for complex geometries but take time to set up and run. Simulate before layout to establish your decoupling strategy, then extract after layout to verify. Always validate against measurements. The gap between simulation and reality shrinks with experience, but never goes to zero.

In complex designs, the regulator-decoupling interaction often dominates PDN performance. Regulators have finite bandwidth and output impedance. Add too much capacitance or caps with very low ESR and you can destabilize the control loop. Load transient response depends on both the regulator bandwidth and the decoupling network; neither alone is sufficient. Point-of-load (POL) regulation brings conversion closer to the load, which reduces distribution losses and improves transient response, but introduces switching noise that needs its own filtering.

If you're dealing with power integrity challenges, whether that's unexplained glitches, voltage droops under transient loads, or anti-resonance issues from your decoupling network, I'd be happy to take a look. I've analyzed and optimized PDN designs for everything from simple microcontroller boards to complex high-speed digital systems.

Sometimes the solution is rearranging capacitor values. Sometimes it's improving the layout to reduce loop inductance. Either way, reach out if you'd like to discuss your situation. Power distribution problems often masquerade as other issues, and identifying them early saves significant debugging time.

Power distribution network design is one of the details that separates reliable hardware from intermittent failures. These techniques are applied across all my power electronics design services.