EMC Best Practices

EMC Best Practices for PCB Layout

EMC problems often surface late because they depend on the complete physical implementation: layout, stackup, enclosure, cables, and grounding. A design can look fine on paper and still fail emissions or immunity once it is assembled and connected to real wiring.

EMC failures are rarely mysterious. They are usually the result of return-current paths, loop areas, high edge rates, and unintended antennas created by cables or plane discontinuities. Most issues are far cheaper to address during layout than after the first hardware build.

The sections below focus on layout practices that reduce emissions and improve immunity in a practical, repeatable way.

The Physics That Causes EMC Problems

Every current creates a magnetic field. Every changing voltage creates an electric field. These fields couple to things you didn't intend: other traces, cables, the enclosure, the air. EMC design is about controlling where those fields go.

Why High Frequencies Cause Problems

At 100 MHz, wavelength is about 3 meters. Once a conductor reaches roughly λ/10 to λ/20 (30 cm down to 15 cm at this frequency, depending on which rule of thumb you use) it starts behaving like an antenna instead of a lumped wire. Your 10 cm trace is in that grey zone; the cable hanging off your board is well past it.

The edge rates of modern digital ICs create harmonics far above the clock frequency. A 10 MHz clock with 1 ns edges has significant energy at 350 MHz. That's why your "low-speed" microcontroller fails radiated emissions at frequencies you never expected.

Loop Area: The Number One EMC Knob

Radiated emissions scale with loop area: $E \propto I \cdot A \cdot f^2$. Double your loop area, double your emissions. Let the frequency double, quadruple your emissions. This is why loop area is the first thing I look at in any EMC review.

That decoupling capacitor 2 cm from your IC? The loop includes those 2 cm of trace. Move it to 2 mm and you've cut the loop area by 10x. This single change has saved designs I've reviewed from EMC failure.

Ground Planes: Don't Break Them

A solid ground plane gives return currents a direct path. Split that plane, and the return current has to go around the slot, creating exactly the large loop area you're trying to avoid.

I've seen designs where someone routed a trace across a ground plane split, then wondered why emissions spiked at a specific frequency. The return current was taking a 5 cm detour. Ground plane cuts for "isolation" often cause more problems than they solve. If you must split, never route high-speed signals across the gap.

Stackup: More Layers Usually Helps

Four layers minimum for anything with clocks above a few MHz. Six layers for serious high-speed work. The cost difference is often less than you'd expect, and a failed EMC test costs far more than the extra layers.

The key is having a solid reference plane immediately adjacent to each signal layer. Signal-Ground-Power-Signal is a reasonable 4-layer stackup. Signal-Ground-Ground-Signal keeps both signal layers referenced to ground, which some designs need. Don't just add layers randomly; design the stackup deliberately.

Differential Pairs: EMC's Best Friend

Equal and opposite currents create fields that cancel. This is why USB, HDMI, Ethernet, and most high-speed interfaces use differential signaling. When done right, the emissions advantage is substantial.

The catch: the cancellation only works if the pair is tightly coupled and length-matched. Spread the traces apart or let one take a different path, and you've converted that nice differential signal into common-mode noise that radiates efficiently.

Power Distribution: Low Impedance at All Frequencies

Your power rail needs to look like a low impedance from DC to hundreds of MHz. Bulk electrolytics handle the low frequencies. MLCCs handle the mid-range. Closely-spaced power and ground planes handle the high end. Miss any of these and you have an impedance peak that creates noise.

Target impedance: $Z_{target} = \frac{V_{ripple}}{I_{transient}}$. If you can tolerate 50mV ripple with 500mA transients, you need under 100mΩ impedance. Plot your PDN impedance versus frequency. Those resonant peaks are where problems hide.

Component Placement: Think in Zones

Put noisy stuff together, quiet stuff together, and keep them apart. Switching regulators in one corner, sensitive analog in another, with digital in between acting as a buffer. Connectors at board edges, not in the middle.

Decoupling capacitors: as close to the IC as physically possible. Every millimeter of trace adds about 1 nH of inductance. At 100 MHz, 10 nH is already 6Ω of impedance, enough to make that capacitor ineffective. Place them like your EMC compliance depends on it, because it does.

Clocks: The Usual Suspect

When a design fails EMC, I check the clock distribution first. Clocks are periodic, so their energy concentrates at harmonics that show up as sharp spikes on the spectrum analyzer. A 25 MHz clock with 1 ns edges has energy up to 350 MHz, so expect to see spikes at 25, 50, 75, 100... all the way up.

Spread spectrum clocking (SSC) smears those spikes across a band, often dropping peak emissions by 10 dB. Most USB and PCIe devices use it. If your spec allows jitter, SSC is an easy win.

Slow Down Those Edges

Your GPIO doesn't need 1 ns edges to toggle an LED. But the chip designer made them fast because someone might need it for something. That unnecessary speed is creating emissions.

A small series resistor (22-33Ω) at the source slows the edge by forming an RC filter with trace and load capacitance. I've fixed EMC failures by adding one-cent resistors to GPIO lines. Check timing margins first, but for many signals you have headroom to spare.

Vias: Don't Forget the Return Path

When your signal goes through a via to another layer, the return current needs a path too. If your signal moves from a layer referenced to ground plane 1 to a layer referenced to ground plane 2, how does the return current get between those planes?

Answer: through nearby stitching vias or capacitors connecting the planes. No nearby path? The return current takes a long detour, creating a large loop. For high-speed signals, place a ground via within 1-2mm of every signal via.

Cables and connectors are often the weakest link for EMC. They make great coupling paths for both conducted and radiated noise. Cables connected to a PCB act as antennas, radiating common-mode currents that flow on the cable shield or among the conductors. These common-mode currents typically come from ground potential differences between connected systems, or from differential-to-common-mode conversion caused by imbalances in the interface circuitry. Filter at cable interfaces, use ferrite cores to increase common-mode impedance, and terminate shields properly. A cable shield is only as good as its transfer impedance, so minimize it through proper connector selection and 360-degree shield termination wherever possible.

EMC filters don't work the same way in every circuit. You have to match the filter to the impedances on each side. A filter that works great in a 50-ohm system may do nothing useful in your actual circuit. Capacitors filter better when the source impedance is high; inductors work better with low source impedances. So the general rule is: put the inductor facing the low-impedance side and the capacitor facing the high-impedance side. For power supply filtering, common-mode chokes work well because they block common-mode noise while letting differential-mode power current through unimpeded. Don't forget parasitics. The self-resonant frequency of capacitors and inductors limits how high in frequency they actually help.

Shield performance depends on material, thickness, and most of all how well the shield is grounded. Even small apertures can hurt shielding, especially when they get close to a significant fraction of the wavelength. You can estimate it: $SE = 20\log_{10}(\frac{\lambda}{2L})$ dB, where $L$ is the longest dimension of the opening. This is why lots of small holes beat one big opening of the same total area. For PCB shield cans, ground them with multiple connections to keep impedance low between the shield and reference plane. Keep the spacing between ground points under $\lambda/20$ at the highest frequency you care about, or the shield edges start acting as slot antennas.

Pre-compliance testing during development catches problems when they're still cheap to fix. Once you understand how your near-field bench measurements relate to far-field compliance results, you can make better design decisions earlier. The usual suspects at the test lab are inadequate filtering at I/O interfaces, poorly grounded cable shields, PDN resonances, and clock harmonics. All of these trace back to PCB layout decisions.

EMC success isn't about applying rules from a checklist. It's about understanding the physics and making informed trade-offs. I've helped products pass certification on the first attempt by addressing EMC concerns during design, and I've helped rescue products that failed by identifying the root causes and implementing targeted fixes.

If you are developing a product that has to pass EMC, get in touch. Designing for compliance from the first layout costs far less than fixing it after fabrication.

EMC compliance is designed in, not bolted on. These best practices are integral to my EMC pre-compliance testing services, from initial layout through pre-compliance testing.