Most PCB tools do one thing. View one place, simulate thermals somewhere else, calculate impedance with a third tool, then chase EMC issues after the prototype comes back. Each one wants its own input format. Each one needs the stackup retyped.
The Salitronic Gerber Analyzer loads the board once and feeds it to every analysis. View it, check the DRC, simulate temperature rise, calculate trace impedance, look at coupled line crosstalk, map the power rail IR drop, even run a quick antenna analysis. All in one browser tab, all on the same loaded design, all free, no signup. Files stay on your machine.
What It Does
Gerber Viewer
Reads Gerber RS-274X and X2, Excellon drill files, ODB++ archives, and IPC-2581. ZIP, RAR, 7z, and TAR archives are extracted automatically. Multi layer 2D rendering with priority stacking, per layer color and visibility, alignment offsets, fit all and flip and rotate views, and step and repeat panel boundaries when present. Pinch to zoom on touch, mm or mil units, and a measurement tool that snaps to vertex, edge, center, and midpoint.
3D Visualization
Realistic 3D PCB with copper, silk, mask, and drill rendered as separate layers. Top, bottom, front, and isometric preset views. X ray toggle makes the substrate translucent so inner copper is visible. Component bodies are inferred from pad and silk geometry, so you get a populated looking board even without a pick and place file.
Stackup Editor
Build your physical stackup: top copper, dielectrics, inner copper, dielectrics, bottom copper. Per layer copper weight in oz, per dielectric thickness, and material from a database that includes FR-4, Polyimide, Rogers 4003C and 4350B, PTFE, and Ceramic. Auto detect button maps parsed Gerber layers into the stack. Standard stackup presets are included. A live Z0 readout shows the impedance of a configurable reference trace width directly in the editor.
Net Trace Tool
Click any copper segment and the connected net is highlighted across layers, walking through vias automatically. Reports total trace length, segment count, pad count, via count, and copper area. The same connectivity engine feeds the impedance probe, the EMI tool, and the antenna analyzer.
Thermal Simulator
Place heat sources on the canvas (point, rectangle, or circle), set the power density, ambient temperature, and convection coefficient, and the solver computes the steady state temperature across every copper layer and dielectric. Vias act as thermal conductance between layers. Results show as a heatmap with optional contour lines and copper outline overlay. Scrub layer slices to see how heat moves through the stack. Live convergence chart while it runs.
Impedance Calculator
Two complementary tools. The Stackup Editor gives a live Z0 readout for a configurable reference trace width on the actual stackup you have built. The Impedance Probe runs a real electromagnetic simulation of any trace you click and reports its characteristic impedance, color coded on the canvas. Microstrip, stripline, and differential pairs are detected automatically. Demo cases for microstrip, CPW, and stripline at 50, 75, and 100 ohms on FR-4 and Rogers are built in for validation.
EMI and Crosstalk Simulator
Pick an aggressor trace and a victim trace by clicking on copper. The tool computes coupled line characteristic impedance, even and odd mode impedance, near end and far end crosstalk over a frequency sweep with magnitude and phase, propagation delay, and a time domain eye diagram at the data rate you specify.
Antenna Analyzer
Pick the antenna trace, the feed point, and a ground reference. The tool returns S11 with a Smith chart style plot, input impedance, radiation efficiency, directivity, and a 3D radiation pattern. The substrate dielectric constant is taken from the stackup so the result reflects your actual board.
Power Integrity (PDN)
Drop VRM and load pins on the power net and the solver computes the DC voltage drop and current density across every copper layer, solving the same board the viewer renders so the powered copper matches what you see highlighted. Results show as an IR drop or current density heatmap with a current flow vector field overlay. Reports worst case IR drop, peak current density, and dissipated power. Multi layer and via aware through the real plated holes. An AC mode sweeps the plane impedance Z(f) with decoupling capacitors. The solve runs in a background worker with live progress and instant cancel.
Design Rule Check
Minimum trace width, minimum clearance, minimum annular ring around drills, edge clearance from the board outline, acid traps, slivers, and isolated copper. Each rule has its own toggle and threshold. Violations are listed with severity, layer, actual versus expected value. Click any violation to zoom to it; the canvas isolates the affected layer automatically.
Gerber Diff
Load a second archive and compare two versions of the board. Layers are auto mapped (basename, extension, inner copper index, kind). Four view modes: A only, B only, overlay (B tinted cyan over A), and XOR diff (red for removed, green for added). Per layer added and removed area is reported in mm squared. Alignment offsets and rotation are configurable for boards that don't share origin.
Pick and Place + BOM
Detects KiCad, Altium, Eagle, JLCPCB, and generic CSV layouts automatically. Loads BOM CSVs alongside, expanding multi designator rows like R1,R2,R3 and merging on designator. Components panel with live token search across designator, value, footprint, manufacturer, MPN, package, and description. Markers on the canvas show each component's position and rotation. When the loaded archive contains a pick and place file, the panel pops open without an extra click.
Drill Analysis and Layer Slicer
Drill map with diameter color coding and a legend table (count, plated versus non plated, round versus slot). Total holes, smallest and largest sizes, plated counts. The Layer Slicer is a slider that scrubs through the stack to reveal one layer at a time, useful for inspecting inner copper without manually toggling visibility.
PCB Spec Sheet Export
Generate a fabrication ready PDF specification sheet from the loaded board in one click. Includes a board summary (dimensions, area, layer count, board thickness), the full layer stackup with materials, copper weights and dielectric constants, a drill and via summary with per diameter counts, and a fabrication constraints table that checks the board's measured minimum trace, clearance, and drill against the capabilities of a chosen fab class (JLCPCB, Eurocircuits, Aisler, AllPCB, and generic IPC tiers). Every number is extracted directly from the uploaded Gerber and Excellon data, and you choose which sections to include.
Who Uses It
- Hardware engineers reviewing a board before tape out, looking for problems that would cost a respin.
- PCB designers sanity checking layouts shared by clients or contractors.
- Hardware startup founders who don't want to license a five figure tool just to verify a contractor's design.
- Manufacturers and assemblers checking customer supplied Gerber packages against their own DFM constraints.
- Educators and students who want a real PCB analysis environment without enterprise software licences.
Related Reading
- PCB Impedance Control: what the impedance probe is computing and why it matters.
- Thermal Management: how to interpret the thermal simulation and design for the result.
- EMC Best Practices: design rules to follow before relying on the EMI simulator.
- Pre Compliance EMC Testing: how the simulator findings map to chamber results.
- PCB Trace Width: current carrying capacity from IPC-2221.
- Design for Testability: what to look for during a board review.
Frequently Asked Questions
What file formats does it accept?
Gerber RS-274X and X2, Excellon drill files, ODB++ archives, and IPC-2581 XML. ZIP, RAR, 7z, and TAR archives are extracted automatically. Pick and place CSVs from KiCad, Altium, Eagle, JLCPCB, and generic exports are detected when present in the archive.
How does the thermal simulator work?
Place heat sources on the canvas as point, rectangle, or circle, set the power density, ambient temperature, and convection coefficient, and the solver computes the steady state temperature across every copper layer and dielectric. Vias are modelled as thermal conductance between layers. Live convergence chart while it runs. Switch layer slices instantly without re simulating.
What does the impedance calculator compute?
Two things. The Stackup Editor gives a live Z0 readout for a configurable reference trace width on the actual stackup you build. The Impedance Probe runs a real electromagnetic simulation of any trace you click and reports its characteristic impedance, color coded on the canvas. Microstrip, stripline, and differential pairs are detected automatically. Demo cases for microstrip, CPW, and stripline at 50, 75, and 100 ohms on FR-4 and Rogers are included for validation.
What does the EMI tool do?
Click an aggressor and a victim trace. The tool computes coupled line characteristic impedance, even and odd mode impedance, near end and far end crosstalk over a frequency sweep, propagation delay, and a time domain eye diagram at the data rate you specify.
What does the antenna analyzer report?
S11 with a Smith chart style plot, input impedance, radiation efficiency, directivity, and a 3D polar radiation pattern. The substrate dielectric constant is taken from the stackup. Pick the antenna trace, the feed point, and a ground reference, and the tool figures out the rest.
Which DRC rules are checked?
Minimum trace width, minimum clearance, minimum annular ring around drills, edge clearance from the board outline, acid traps, slivers, and isolated copper. Each rule has its own toggle and threshold. Click a violation to zoom to it; the canvas auto isolates the affected layer.
Can I compare two versions of a Gerber?
Yes. Load a second archive in the Diff tool. Layers are auto mapped, and four views are available: A only, B only, overlay (B tinted cyan over A), and XOR (red for removed, green for added). Per layer added and removed area is reported in mm squared. Alignment offsets and rotation are configurable for boards that don't share origin.
Can I export a fabrication spec sheet?
Yes. Once a board is loaded, the Spec button generates a multi page PDF specification sheet. It covers the board summary, the full layer stackup, a drill and via breakdown, and a fabrication constraints table that flags any feature finer than your selected fab class. You set the project name, revision, and fab class, and pick which sections to include. The data is read straight from the uploaded artwork, so it matches what the viewer shows.
Are my files uploaded to a server?
No. Everything runs locally in your browser. Your design files never leave your machine.
Is there an API or downloadable version?
Not currently. The tool is web only. If you need API access for batch processing or self hosting for sensitive projects, reach out via the contact page.